DFM Checklist

Design and Component Selection: Each component is or will be readily available in production quantities. Minimize number and variety of different components. No components at end-of-life designed in. No sole-source devices, if possible. Multiple manufacturers specified for components. Second sources checked for mechanical and electrical fit. Component tolerance issues analyzed. Component temperature ranges considered. Use a BGA instead of that huge fine-pitch QFP. Eliminate trim pots. Design for Environment: recycle, reuse, and repair.

General Layout Considerations: Visible orientation marks for all polarized components on the silkscreen layer. Polarized components (e.g., capacitors) oriented the same direction. Workmanship requirements established, e.g., IPC. Number of processes minimized. Hand soldering minimized. Hand insertion and assembly minimized.

Through-Hole Components: Unplated tooling holes for through-hole automation. Drill sizes should be lead diameter +0.015”. DIP socket drill holes should be 0.040”. Components positioned at 0, 90, 180, or 270 degrees. Component layout optimized for auto insertion. DIPs oriented the same way on volume boards. Axials oriented the same way on volume boards. TO-92 layouts are inline spaced 0.100” pad-to-pad. No stand-up axial components. Minimum 0.010” annular rings on through-hole pads.

SMT Land Patterns: Fine-pitch land patterns at 60% pad width/pitch. Land patterns match actual physical components. Use of land patterns optimized for manufacture. No natural bridges on fine-pitch SMT. Non-solder mask defined (NSMD) pads for BGAs.

Wave-Soldered Bottom-Side SMT Components: Evaluate the need for this lower-yielding process. SMT wave land patterns optimized. Component orientation optimized for wave. No 4-sided SMT or fine-pitch SMT components. Minimum component-to-component spacing is the height of the tallest component. Other wave solder shadowing considerations. On mixed technology PCBs, no SMT components on the bottom within the DIP clinch head footprint.

Hardware: Use stainless steel when PCB contact is made. Favor Torx drive screws for ease of assembly. Minimize the number of different screw sizes and styles; prioritize commonality. Torque values are specified for screws and nuts. Silpad washers on power devices where required. Mounting holes should be unplated with no pads if possible.

Board Mechanicals: Three fiducial marks, each 0.060”, on each side with SMT. Via holes covered with solder mask as the normal strategy except for some ICT-enabled designs. Layer stack-up identification on the board or breakaway. Component-to-board edge clearance considerations. Panelization or breakouts discussed with AB Electronics.

Board Specifications: Optimal board finish specified (e.g., ENIG for boards with μBGA or QFPs 0.020” pitch and smaller). Boards specified for Bare-Board Test (BBT). Gerber files generated in RS-274-X format. No solder mask between fine-pitch 0.020” or smaller. Controlled impedance specified where required. Any special board materials or construction specified for high-frequency boards. SMT Paste layer(s) with no fiducial or other parts. Ensure post-breakout PCB dimensions and dimensional tolerances are accounted for in the panel design.

Test Strategy: Test plan established before the design starts. Failure modes considered. Choose among self-test, manual functional test, boundary-scan board test, automated functional test, and in-circuit/combination test (ICT). Avoid test turrets and hooks; use SMT loops where on-board test pads are not feasible.

In-Circuit Test Mini-Checklist: Schematic review by AB Electronics test engineers prior to board layout. Enables for ICs and oscillators with resistor pull-downs. Unused IC pins for complex ICs have test pads. Proper circuit layout for boundary scan devices. One test pad per net, accessible from the bottom. More pads for power nets: 0.5A per test point. Minimum test pad size is 0.030”; prefer 0.040” square. Through-hole leads used as test points are acceptable. Two tooling holes required: diagonally opposite, minimum 0.093”, 0.125” preferred – unplated. Use of 0.050” and 0.075” center-to-center test points minimized or eliminated; 0.100” spacing preferred. Pads with via holes used as test points have no solder mask over them; other vias are masked. ICT tooling hole-to-test pad clearance: 0.125”. Board edge-to-test pad clearance: 0.100”. On-board batteries have disconnect jumpers.